DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 362
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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Section 12 8-Bit Timer (TMR)
Counter Clear Specification:
Pin Output:
12.6.2
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match
A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the
CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for each channel.
12.7
TMR_X has input capture registers (TICR, TICRR and TICRF). A narrow pulse width can be
measured with TICRR and TICRF, using a single capture operation controlled by the ICST bit in
TCONRI of the timer connection. If the falling edge of TMRIX is detected after its rising edge has
been detected while the ICST bit is set to 1, the value of TCNT at that time is transferred to both
TICRR and TICRF, and the ICST bit is cleared to 0.
The input signal to TMRIX can be switched by the setting of the other bits in TCONRI.
Rev. 3.00 Mar 21, 2006 page 306 of 788
REJ09B0300-0300
If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the
16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-match
occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear
by the TMI0 pin has been set.
The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
16-bit compare-match conditions.
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
lower 8-bit compare-match conditions.
Compare-Match Count Mode
Input Capture Operation
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