DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 37
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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23.8 Flash Memory Programming/Erasing ............................................................................... 623
23.9 Program/Erase Protection ................................................................................................. 628
23.10 Interrupts during Flash Memory Programming/Erasing ................................................... 629
23.11 Programmer Mode ............................................................................................................ 630
23.12 Usage Notes ...................................................................................................................... 631
Section 24 Clock Pulse Generator
24.1 Oscillator........................................................................................................................... 634
24.2 Duty Correction Circuit .................................................................................................... 637
24.3 Medium-Speed Clock Divider .......................................................................................... 637
24.4 Bus Master Clock Select Circuit ....................................................................................... 638
24.5 Subclock Input Circuit ...................................................................................................... 638
24.6 Subclock Waveform Forming Circuit ............................................................................... 639
24.7 Clock Select Circuit .......................................................................................................... 639
24.8 Processing for X1 and X2 Pins ......................................................................................... 640
24.9 Usage Notes ...................................................................................................................... 640
Section 25 Power-Down Modes
25.1 Register Descriptions ........................................................................................................ 641
25.2 Mode Transitions and LSI States ...................................................................................... 646
25.3 Medium-Speed Mode........................................................................................................ 649
25.4 Sleep Mode ....................................................................................................................... 650
25.5 Software Standby Mode.................................................................................................... 651
25.6 Hardware Standby Mode .................................................................................................. 652
25.7 Watch Mode...................................................................................................................... 653
25.8 Subsleep Mode.................................................................................................................. 654
25.9 Subactive Mode ................................................................................................................ 655
23.7.1 Boot Mode ........................................................................................................... 618
23.7.2 User Program Mode............................................................................................. 622
23.8.1 Program/Program-Verify ..................................................................................... 624
23.8.2 Erase/Erase-Verify............................................................................................... 626
23.9.1 Hardware Protection ............................................................................................ 628
23.9.2 Software Protection.............................................................................................. 628
23.9.3 Error Protection.................................................................................................... 628
24.1.1 Connecting Crystal Resonator ............................................................................. 634
24.1.2 External Clock Input Method............................................................................... 635
24.9.1 Note on Resonator ............................................................................................... 640
24.9.2 Notes on Board Design ........................................................................................ 640
25.1.1 Standby Control Register (SBYCR) .................................................................... 642
25.1.2 Low-Power Control Register (LPWRCR) ........................................................... 644
25.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 645
...................................................................................... 641
.................................................................................. 633
Rev. 3.00 Mar 21, 2006 page xxxv of liv
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