DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 422
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
- Current page: 422 of 847
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Section 15 Serial Communication Interface (SCI and IrDA)
15.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared.
Bit
7
6
5
Rev. 3.00 Mar 21, 2006 page 366 of 788
REJ09B0300-0300
Bit Name
TDRE
RDRF
ORER
Serial Status Register (SSR)
Initial Value
1
0
0
R/W
R/(W) *
R/(W) *
R/(W) *
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared to
0.
Overrun Error
[Setting condition]
When the next data is received while RDRF = 1
[Clearing condition]
When 0 is written to ORER after reading
ORER = 1
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and
TDR is ready for data write
When 0 is written to TDRE after reading
TDRE = 1
When a TXI interrupt request is issued allowing
the DTC to write data to TDR
RDRF = 1
When an RXI interrupt request is issued allowing
the DTC to read data from RDR
When 0 is written to RDRF after reading
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