DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 464
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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Section 15 Serial Communication Interface (SCI and IrDA)
Reception: Before making a transition to module stop, software standby, watch, sub-active, or
sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made
during data reception, the data being received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 15.27 shows a sample flowchart for mode transition during reception.
Rev. 3.00 Mar 21, 2006 page 408 of 788
REJ09B0300-0300
Figure 15.24 Sample Flowchart for Mode Transition during Transmission
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
Read TEND flag in SSR
All data transmitted?
Start transmission
Transmission
Initialization
TEND = 1
Yes
Yes
Yes
TE = 0
[2]
No
No
No
TE = 1
[1]
[3]
[1] Data being transmitted is lost
[2] Also clear TIE and TEIE to 0
[3] Module stop, watch, sub-active,
halfway. Data can be normally
transmitted from the CPU by
setting TE to 1, reading SSR,
writing to TDR, and clearing
TDRE to 0 after mode
cancellation; however, if the DTC
has been initiated, the data
remaining in DTC RAM will be
transmitted when TE and TIE are
set to 0.
when they are 1.
and sub-sleep modes are
included.
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