DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 469

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

The I
optional function.
This LSI has a two-channel I
subset of the Philips I
controls the I
16.1
IFIIC60A_000020020700
Although the product type name is identical, please contact Renesas before using this optional
function on an F-ZTAT version product.
Selection of addressing format or non-addressing format
Conforms to Philips I
Two ways of setting slave address (I
Start and stop conditions generated automatically in master mode (I
Selection of the acknowledge output level in reception (I
Automatic loading of an acknowledge bit in transmission (I
Wait function in master mode (I
Wait function (I
Interrupt sources
2
C bus interface is provided as an optional function. Note the following point when using this
I
Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
master operation only
Formatless (for IIC_0 only): non-addressing format with a clock pin dedicated for
formatless; for slave operation only
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
The wait can be cleared by clearing the interrupt flag.
A wait request can be generated by driving the SCL pin low after data transfer.
The wait request is cleared when the next transfer becomes possible.
Data transfer end (including when a transition to transmit mode with I
when ICDR data is transferred, or during a wait state)
2
C bus format: addressing format with an acknowledge bit, for master/slave operation
Features
Section 16 I
2
C bus differs partly from the Philips configuration, however.
2
C bus format)
2
C bus (inter-IC bus) interface functions. The register configuration that
2
C bus interface (I
2
C bus interface. The I
2
C Bus Interface (IIC) (Optional)
2
C bus format)
2
C bus format)
2
C bus format)
2
C bus interface conforms to and provides a
Section 16 I
Rev. 3.00 Mar 21, 2006 page 413 of 788
2
C bus format)
2
C bus format)
2
C Bus Interface (IIC) (Optional)
2
C bus format)
2
C bus format occurs,
REJ09B0300-0300