DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 483
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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Bit Bit Name
1
IRIC
Initial Value R/W
0
R/(W) * I
Description
Indicates that the I
request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See
section 16.4.7, IRIC Setting Timing and SCL Control. The
conditions under which IRIC is set also differ depending on
the setting of the ACKE bit in ICCR.
[Setting conditions]
I
I
2
2
2
C Bus Interface Interrupt Request Flag
C bus format master mode:
C bus format slave mode:
When a start condition is detected in the bus line state
after a start condition is issued (when the ICDRE flag is
set to 1 because of first frame transmission)
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the 8th
transmit/receive clock)
At the end of data transfer (rise of the 9th
transmit/receive clock while no wait is inserted)
When a slave address is received after bus arbitration
is lost (the first frame after the start condition)
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) when the ACKE bit is 1
When the AL flag is set to 1 after bus arbitration is lost
while the ALIE bit is 1
When the slave address (SVA or SVAX) matches
(when the AAS or AASX flag in ICSR is set to 1) and at
the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (rise of the 9th transmit/receive clock)
When the general call address is detected (when 0 is
received as the R/W bit and the ADZ flag in ICSR is set
to 1) and at the end of data reception up to the
subsequent retransmission start condition or stop
condition detection (rise of the 9th receive clock)
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) while the ACKE bit is 1
When a stop condition is detected (when the STOP or
ESTP flag in ICSR is set to 1) while the STOPIM bit is 0
Section 16 I
Rev. 3.00 Mar 21, 2006 page 427 of 788
2
C bus interface has issued an interrupt
2
C Bus Interface (IIC) (Optional)
REJ09B0300-0300
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