DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 485
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified
number of ICDR reads or writes have been completed.
Tables 16.4 and 16.5 show the relationship between the flags and the transfer states.
Table 16.4 Flags and Transfer States (Master Mode)
Legend:
0:
1:
—: Previous state retained
0 : Cleared to 0
1 : Set to 1
MST
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0-state retained
1-state retained
TRS
1
1
—
1
1
1
1
1
1
0
0
0
0
0
0
—
BBSY
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
ESTP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STOP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IRTR
0
1
—
—
1
—
—
—
1
1
—
—
—
1
—
—
AASX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AAS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 16 I
Rev. 3.00 Mar 21, 2006 page 429 of 788
ACKB
0
0
—
1
0
0
0
0
0
—
—
—
—
—
—
—
ICDRF
—
—
—
—
—
—
—
—
—
1
0
1
0
1
—
—
2
C Bus Interface (IIC) (Optional)
ICDRE
0
1
—
—
1
0
1
0
1
—
—
—
—
—
—
0
State
Idle state (flag clearing
required)
Start condition detected
Wait state
Transmission end
(ACKE=1 and ACKB=1)
Transmission end with
ICDRE=0
ICDR write with the above
state
Transmission end with
ICDRE=1
ICDR write with the above
state or after start
condition detected
Automatic data transfer
from ICDRT to ICDRS with
the above state
Reception end with
ICDRF=0
ICDR read with the above
state
Reception end with
ICDRF=1
ICDR read with the above
state
Automatic data transfer
from ICDRS to ICDRR
with the above state
Arbitration lost
Stop condition detected
REJ09B0300-0300
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