DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 508
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
- Current page: 508 of 847
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Section 16 I
Rev. 3.00 Mar 21, 2006 page 452 of 788
REJ09B0300-0300
Figure 16.14 Sample Flowchart for Operations in Master Receive Mode
2
C Bus Interface (IIC) (Optional)
No
No
No
Set BBSY= 0 and SCP= 0
Wait for one clock pulse
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Set HNDS = 0 in ICXR
Set ACKB = 0 in ICSR
Clear IRIC flag in ICCR
Set WAIT = 1 in ICMR
Read IRIC flag in ICCR
Set ACKB = 1 in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Set WAIT = 0 in ICMR
Set TRS = 0 in ICCR
Master receive mode
Set TRS = 1 in ICCR
(Receiving Multiple Bytes) (WAIT = 1)
Last receive?
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRIC = 1?
IRTR=1?
IRIC=1?
in ICCR
End
Yes
Yes
Yes
No
No
Yes
Yes
[16] Read the last receive data.
[17] Generate stop condition
[1] Select receive mode.
[2] Start receiving. The first read
[3] Wait for a receive wait
[5] Read the receive data.
[6] Clear IRIC flag.
[7] Set acknowledge data for the last reception.
[8] Wait for TRS setting
[9] Set TRS for stop condition issuance
[10] Read the receive data.
[11] Clear IRIC flag. (to end the wait insertion)
[12] Wait for a receive wait
[13] Determine end of reception
[14] Clear IRIC.
[15] Clear wait mode.
[4] Determine end of reception
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
is a dummy read.
(to end the wait insertion)
(to end the wait insertion)
Clear IRIC flag.
( IRIC flag should be cleared to 0
after setting WAIT = 0.)
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