DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 515
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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The reception procedure and operations using the HNDS bit function, by which data reception
process is provided in 1-byte unit with SCL being fixed low at every data reception, are described
below.
1. Initialize the IIC as described in section 16.4.2, Initialization.
2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
4. When the slave address matches in the first frame following the start condition, the device
5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0.
9. If the next frame is the last receive frame, set the ACKB bit to 1.
10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the
Receive operations can be performed continuously by repeating steps [5] to [10].
11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the
12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the
ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
the IRIC flag to 0.
to 1. The master device then outputs the 7-bit slave address and transmit/receive direction
(R/W), in synchronization with the transmit clock pulses.
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit
(R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
as an acknowledge signal.
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, IRTR flag is also set to 1.
setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive
clock pulse until data is read from ICDR.
master device to transfer the next data.
BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to
0, the IRIC flag is set to 1.
Section 16 I
Rev. 3.00 Mar 21, 2006 page 459 of 788
2
C Bus Interface (IIC) (Optional)
REJ09B0300-0300
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