DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 53

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

Table 15.9
Table 15.10 IrCKS2 to IrCKS0 Bit Settings .............................................................................. 404
Table 15.11 SCI Interrupt Sources ............................................................................................. 405
Section 16 I
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Table 16.9
Table 16.10 Permissible SCL Rise Time (t
Table 16.11 I
Section 17 Keyboard Buffer Controller
Table 17.1
Section 18 Host Interface X-Bus Interface (XBS)
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 18.9
Section 19 Host Interface LPC Interface (LPC)
Table 19.1
Table 19.2
Table 19.3
Table 19.4
Table 19.5
Table 19.6
Table 19.7
Table 19.8
SSR Status Flags and Receive Data Handling........................................................ 384
Pin Configuration ................................................................................................... 416
Communication Format.......................................................................................... 420
I
Flags and Transfer States (Master Mode) .............................................................. 429
Flags and Transfer States (Slave Mode)................................................................. 430
I
Examples of Operation Using DTC ....................................................................... 472
IIC Interrupt Sources.............................................................................................. 475
I
Pin Configuration ................................................................................................... 491
Pin Configuration ................................................................................................... 511
Set/Clear Timing for STR Flags............................................................................. 519
Host Interface Channel Selection and Pin Operation ............................................. 520
Host Interface Operations from HIF Host, and Slave Operation............................ 521
GA20 (P81) Set/Clear Timing................................................................................ 522
Fast A20 Gate Output Signal.................................................................................. 523
Scope of HIF Pin Shutdown................................................................................... 524
Input Buffer Full Interrupts .................................................................................... 525
HIRQ Setting/Clearing Conditions......................................................................... 526
Pin Configuration ................................................................................................... 531
Register Selection................................................................................................... 544
GA20 (P81) Set/Clear Timing................................................................................ 565
Scope of Host Interface Pin Shutdown................................................................... 569
Scope of Initialization in Each Host Interface Mode.............................................. 570
Receive Complete Interrupts and Error Interrupt ................................................... 575
HIRQ Setting and Clearing Conditions.................................................................. 576
2
Fast A20 Gate Output Signals ............................................................................... 567
2
2
2
2
C Bus Interface (IIC) (Optional)
C Transfer Rate .................................................................................................... 423
C Bus Data Format Symbols................................................................................ 443
C Bus Timing (SCL and SDA Outputs)............................................................... 476
C Bus Timing (with Maximum Influence of t
sr
) Values ................................................................. 477
Sr
/t
Rev. 3.00 Mar 21, 2006 page li of liv
Sf
)............................................... 478