HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 409
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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Quantity:
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Company:
Part Number:
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Manufacturer:
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Quantity:
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Part Number:
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11.2.6 Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP
TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of
NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or
different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3
and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be
modified and always read 1.
Address H'FFA4
Address H'FFA6
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
15
NDR15
NDR15
to TP
R/W
R/W
—
—
7
0
7
0
7
1
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Next data 15 to 12
These bits store the next output
data for TPC output group 3
8
). During TPC output, when an ITU compare match event specified in
NDR14
NDR14
R/W
R/W
—
—
6
6
0
0
6
1
NDR13
NDR13
R/W
R/W
—
—
5
5
0
0
5
1
389
NDR12
NDR12
Reserved bits
R/W
R/W
—
—
4
0
4
0
4
1
NDR11
NDR11
R/W
R/W
—
—
3
0
3
0
3
1
Next data 11 to 8
Next data 11 to 8
These bits store the next output
These bits store the next output
data for TPC output group 2
data for TPC output group 2
NDR10
NDR10
R/W
R/W
—
—
2
2
0
0
2
1
NDR9
NDR9
R/W
R/W
—
—
1
0
1
0
1
1
NDR8
NDR8
R/W
R/W
—
—
0
0
0
0
0
1
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