HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 485
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Company:
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Receiving Multiprocessor Serial Data: Figure 13-12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
No
No
No
Read ORER and FER flags in SSR
Read ORER and FER flags in SSR
Figure 13-12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
Read receive data from RDR
Read receive data from RDR
Set MPIE bit to 1 in SCR
Read RDRF flag in SSR
Read RDRF flag in SSR
Clear RE bit to 0 in SCR
Finished receiving?
FER
FER
Start receiving
RDRF = 1?
RDRF = 1?
Own ID?
Initialize
End
PRER = 1
ORER = 1
No
Yes
Yes
No
Yes
No
Yes
Yes
Yes
3
1
2
No
(continued on next page)
Error handling
4
465
5
1.
2.
3.
4.
5.
SCI initialization: the receive data function
of the RxD pin is selected automatically.
ID receive cycle: set the MPIE bit to 1 in SCR.
SCI status check and ID check: read SSR,
check that the RDRF flag is set to 1, then read
data from RDR and compare with the
processor’s own ID. If the ID does not match,
set the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches, clear the
RDRF flag to 0.
SCI status check and data receiving: read
SSR, check that the RDRF flag is set to 1,
then read data from RDR.
Receive error handling and break detection:
if a receive error occurs, read the
ORER and FER flags in SSR to identify the error.
After executing the necessary error handling,
clear the ORER and FER flags both to 0.
Receiving cannot resume while either the ORER
or FER flag remains set to 1. When a framing
error occurs, the RxD pin can be read to detect
the break state.
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