HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 61
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Company:
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead
of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2-11 Addressing Modes
No.
1
2
3
4
5
6
7
8
Addressing Mode
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
41
Symbol
Rn
@ERn
@(d:16, ERn)/@d:24, ERn)
@ERn+
@–ERn
@aa:8/@aa:16/@aa:24
#xx:8/#xx:16/#xx:32
@(d:8, PC)/@(d:16, PC)
@@aa:8
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