HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 80
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Company:
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3003.
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 17, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7
SSBY
0
1
Bit
Initial value
Read/Write
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
SSBY
Software standby
Enables transition to software standby mode
R/W
7
0
STS2
R/W
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
6
0
STS1
R/W
5
0
60
STS0
R/W
4
0
User bit enable
Selects whether to use UI bit in CCR 6
as a user bit or an interrupt mask bit
R/W
UE
3
1
NMI edge select
Selects the valid edge
of the NMI input
NMIEG
R/W
2
0
Reserved bit
—
—
1
1
RAM enable
Enables or
disables
on-chip RAM
(Initial value)
RAME
R/W
0
1
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