HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 172

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
296
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
784
Section 2 Instruction Descriptions
2.2.44 (2)
NEG (NEGate)
Operation
0 – Rd
Assembly-Language Format
NEG.W Rd
Operand Size
Word
Description
This instruction takes the two’s complement of the contents of a 16-bit register Rd (destination
operand) and stores the result in the 16-bit register Rd (subtracting the register contents from
H'0000). If the original contents of Rd were H'8000, however, the result remains H'8000.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
An overflow occurs if the original contents of Rd were H'8000.
Rev. 4.00 Feb 24, 2006 page 156 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
Rd
NEG (W)
Mnemonic
NEG.W
Operands
Rd
1st byte
1
7
Condition Code
H: Set to 1 if there is a borrow at bit 11;
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Set to 1 if there is a borrow at bit 15;
2nd byte
9
Instruction Format
otherwise cleared to 0.
cleared to 0.
cleared to 0.
cleared to 0.
otherwise cleared to 0.
I
rd
UI H
3rd byte
U
Negate Binary Signed
N
4th byte
Z
V
States
No. of
C
1