M306N4FCGP#U3 Renesas Electronics America, M306N4FCGP#U3 Datasheet
M306N4FCGP#U3
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M306N4FCGP#U3 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M16C/6N Group (M16C/6N4) Renesas MCU 1. Overview The M16C/6N Group (M16C/6N4) of MCUs are built using the high-performance silicon gate CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These MCUs ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1.2 Performance Overview Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N4). Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N4) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1.3 Block Diagram Figure 1.1 shows a Block Diagram. 8 Port P0 Internal peripheral functions Timer (16 bits) Output (timer A): 5 Input ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1.4 Product Information Table 1.2 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages. Table 1.2 Product ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1.5 Pin Assignments Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.3 and 1.4 list the List of Pin Names. ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) P1_2/D10 76 P1_1/ P1_0/D8 P0_7/AN0_7/D7 79 P0_6/AN0_6/D6 80 P0_5/AN0_5/ P0_4/AN0_4/D4 83 P0_3/AN0_3/D3 84 P0_2/AN0_2/D2 85 P0_1/AN0_1/D1 86 P0_0/AN0_0/D0 87 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 1.3 List of Pin Names (1) Pin No. Control Interrupt Port FP GP Pin Pin 1 99 P9_6 2 100 P9_5 3 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 1.4 List of Pin Names (2) Pin No. Control Interrupt Port FP GP Pin Pin 51 49 P4_3 52 50 P4_2 53 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1.6 Pin Functions Tables 1.5 to 1.7 list the Pin Functions. Table 1.5 Pin Functions (1) Signal Name Pin Name Power supply VCC1, ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 1.6 Pin Functions (2) Signal Name Pin Name Main clock XIN input Main clock XOUT output Sub clock XCIN input Sub clock ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 1.7 Pin Functions (3) Signal Name Pin Name I/O port P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 2.3 Frame Base Register (FB configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 3. Memory Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) An SFR (Special Function Register control register for a peripheral function. Tables 4.1 to 4.16 list ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.2 SFR Information (2) Address 0040h CAN0/1 Wake-up Interrupt Control Register 0041h CAN0 Successful Reception Interrupt Control Register 0042h CAN0 Successful Transmission ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.3 SFR Information (3) Address 0080h 0081h 0082h CAN0 Message Box 2: Identifier / DLC 0083h 0084h 0085h 0086h 0087h 0088h 0089h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.4 SFR Information (4) Address 00C0h 00C1h 00C2h CAN0 Message Box 6: Identifier / DLC 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.5 SFR Information (5) Address 0100h 0101h 0102h CAN0 Message Box 10: Identifier / DLC 0103h 0104h 0105h 0106h 0107h 0108h 0109h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.6 SFR Information (6) Address 0140h 0141h 0142h CAN0 Message Box 14: Identifier /DLC 0143h 0144h 0145h 0146h 0147h 0148h 0149h CAN0 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.7 SFR Information (7) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.8 SFR Information (8) Address 01C0h Timer B3, B4, B5 Count Start Flag 01C1h 01C2h Timer A1-1 Register 01C3h 01C4h Timer A2-1 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.9 SFR Information (9) Address 0200h CAN0 Message Control Register 0 CAN0 Message Control Register 1 0201h CAN0 Message Control Register 2 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.10 SFR Information (10) Address 0240h 0241h 0242h CAN0 Acceptance Filter Support Register 0243h 0244h CAN1 Acceptance Filter Support Register 0245h 0246h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.11 SFR Information (11) Address 0280h 0281h 0282h CAN1 Message Box 2: Identifier / DLC 0283h 0284h 0285h 0286h 0287h 0288h 0289h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.12 SFR Information (12) Address 02C0h 02C1h 02C2h CAN1 Message Box 6: Identifier / DLC 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.13 SFR Information (13) Address 0300h 0301h 0302h CAN1 Message Box 10: Identifier / DLC 0303h 0304h 0305h 0306h 0307h 0308h 0309h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.14 SFR Information (14) Address 0340h 0341h 0342h CAN1 Message Box 14: Identifier / DLC 0343h 0344h 0345h 0346h 0347h 0348h 0349h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.15 SFR Information (15) Address 0380h Count Start Flag 0381h Clock Prescaler Reset Flag One-Shot Start Flag 0382h Trigger Select Register 0383h ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 4.16 SFR Information (16) Address 03C0h A/D Register 0 03C1h 03C2h A/D Register 1 03C3h 03C4h A/D Register 2 03C5h 03C6h A/D ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electrical Characteristics 5.1 Electrical Characteristics (T/V-ver.) Table 5.1 Absolute Maximum Ratings Symbol Parameter Supply voltage (VCC1 = VCC2 Analog ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.2 Recommended Operating Conditions (1) Symbol V Supply voltage (VCC1 = VCC2 Analog supply voltage CC V Supply voltage SS ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.3 Recommended Operating Conditions (2) Symbol f(XIN) Main clock input oscillation No wait Mask ROM version VCC = 4.2 to 5.5 V ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.4 Electrical Characteristics (1) Symbol Parameter V HIGH output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, OH voltage P3_0 to ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.5 Electrical Characteristics (2) Symbol Parameter I Power supply In single-chip mode, CC current the output pins are (VCC = 4.2 to ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.6 A/D Conversion Characteristics Symbol Parameter – Resolution INL Integral 10 bits nonlinearity error 8 bits – Absolute 10 bits accuracy 8 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.8 Power Supply Circuit Timing Characteristics Symbol t Time for internal power supply stabilization during powering-on d(P-R) t STOP release time d(R-S) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 5 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.9 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 5 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.11 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 5 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.17 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 5 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 5 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 5 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) XIN input t r TAiIN input TAiOUT input TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK t d(BCLK-CS) 25ns.max CSi tcyc t d(BCLK-AD) 25ns.max ADi ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK t d(BCLK-CS) 25ns.max CSi tcyc t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK t d(BCLK-CS) 25ns.max CSi t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK t d(BCLK-CS) 25ns.max CSi t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK t d(BCLK-CS) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK t d(BCLK-CS) 25ns.max ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5.2 Electrical Characteristics (Normal-ver.) Table 5.26 Absolute Maximum Ratings Symbol Parameter Supply voltage (VCC1 = VCC2 Analog supply voltage CC ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.27 Recommended Operating Conditions (1) Symbol V Supply voltage (VCC1 = VCC2 Analog supply voltage CC V Supply voltage SS ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.28 Recommended Operating Conditions (2) Symbol f(XIN) Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.29 A/D Conversion Characteristics Symbol Parameter – Resolution INL Integral 10 bits nonlinearity error 8 bits – Absolute 10 bits accuracy 8 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.31 Power Supply Circuit Timing Characteristics Symbol t Time for internal power supply stabilization during powering-on d(P-R) t STOP release time d(R-S) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.32 Electrical Characteristics (1) Symbol Parameter V HIGH output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, OH voltage P3_0 to ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.33 Electrical Characteristics (2) Symbol Parameter I Power supply In single-chip mode, CC current the output pins are (VCC = 3.0 to ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 5 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.34 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 5 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.36 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 5 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.42 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 5 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 5 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 5 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) XIN input t r TAiIN input TAiOUT input TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK t d(BCLK-CS) 25ns.max CSi tcyc t d(BCLK-AD) 25ns.max ADi ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK t d(BCLK-CS) 25ns.max CSi tcyc t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK t d(BCLK-CS) 25ns.max CSi t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK t d(BCLK-CS) 25ns.max CSi t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK t d(BCLK-CS) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK t d(BCLK-CS) 25ns.max ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.51 Electrical Characteristics Symbol Parameter V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, HIGH output OH voltage P3_0 to P3_7, ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 3.3 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.52 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 3.3 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.54 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Timing Requirements (Referenced to VCC = 3.3 V, VSS = Topr = –40 to 85°C unless otherwise specified) Table 5.60 ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 3.3 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 3.3 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Switching Characteristics (Referenced to VCC = 3.3 V, VSS = Topr = – °C unless otherwise specified) Table ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) XIN input t r TAiIN input TAiOUT input TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK t d(BCLK-CS) 30ns.max CSi tcyc t d(BCLK-AD) 30ns.max ADi ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK t d(BCLK-CS) 30ns.max CSi tcyc t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK t d(BCLK-CS) 30ns.max CSi t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK t d(BCLK-CS) 30ns.max CSi t d(BCLK-AD) ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK t d(BCLK-CS) 40ns.max CSi ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK t d(BCLK-CS) 40ns.max ...
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Appendix 1. Package Dimensions JEITA Package Code RENESAS Code P-QFP100-14x20-0.65 PRQP0100JB 100 1 Index mark Z D ...
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REVISION HISTORY Rev. Date Page 1.00 Jun. 30, 2003 – First edition issued 2.00 Nov. 10, 2004 – Revised edition issued * Words standardizes (on-chip oscillator) * 100P6Q-A (100-pin version) is added. * Revised parts and revised contents are as ...
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REVISION HISTORY Rev. Date Page 2.00 Nov. 10, 2004 34 Table 5.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added. 35 Table 5.8 Power Supply Circuit Timing Characteristics: "t Figure 5.2 Power Supply Circuit Timing Diagram is added. 36 Table ...
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REVISION HISTORY Rev. Date Page 2.40 Aug. 25, 2006 7, 8 Tables 1.3 and 1.4 List of Pin Names (1)(2) are added. 9 Table 1.5 Pin Functions (1) • 3.0 to 5.5 V (Normal-ver.) is added to Description of Power ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...