DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 238
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Data Transfer Controller (DTC)
The interrupt source flag for RXI0, for example, is the RDRF flag in SCI0.
Table 7.3
Activation
Source
Software
activation
Interrupt
activation
Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC is activated in accordance with the default priorities.
Rev. 4.00 Sep 27, 2006 page 192 of 1130
REJ09B0327-0400
Source flag cleared
IRQ interrupt
supporting
DTVECR
On-chip
module
Activation Sources and DTCER Clearing
Figure 7.3 Block Diagram of DTC Activation Source Control
When DISEL Bit Is 0 and
Specified Number of Transfers
Have Not Ended
SWDTE bit cleared to 0
Interrupt
request
Corresponding DTCER bit held
at 1
Activation source flag cleared
to 0
DTCER
Select
Clear
Interrupt controller
control
When DISEL Bit Is 1 or
Specified Number of Transfers
Have Ended
Clear
DTC
SWDTE bit held at 1
Interrupt request sent to CPU
Corresponding DTCER bit cleared to 0
Activation source flag held at 1
Activation source interrupt request
sent to CPU
Clear request
Interrupt mask
CPU
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