DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 482
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 Serial Communication Interface (SCI, IrDA)
external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out
before the SCI’s operating mode is determined using SMR.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Bit 1
CKE1
0
1
Notes: 1. Initial value
15.2.7
Note:
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
Rev. 4.00 Sep 27, 2006 page 436 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
* Only 0 can be written, to clear the flag.
Serial Status Register (SSR)
Bit 0
CKE0
0
1
0
1
R/(W) *
TDRE
Description
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
7
1
R/(W) *
RDRF
6
0
R/(W) *
ORER
5
0
Internal clock/SCK pin functions as I/O port *
Internal clock/SCK pin functions as serial clock
output *
Internal clock/SCK pin functions as clock output *
Internal clock/SCK pin functions as serial clock
output
External clock/SCK pin functions as clock input *
External clock/SCK pin functions as serial clock
input
External clock/SCK pin functions as clock input *
External clock/SCK pin functions as serial clock
input
R/(W) *
FER
4
0
1
R/(W) *
PER
3
0
TEND
R
2
1
MPB
R
1
0
MPBT
R/W
0
0
1
3
3
2
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