DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 545
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
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Price
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Part Number:
DF2148ATE20IV
Manufacturer:
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Quantity:
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Part Number:
DF2148ATE20IV
Manufacturer:
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16.2.2
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I
Bit 0—Format Select (FS): Used together with the FSX bit in SARX and the SW bit in
DDCSWR to select the communication format.
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode.
Bit
Initial value
Read/Write
I
Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
Formatless mode (channel 0 only): non-addressing format with or without acknowledge bit,
slave mode only, start/stop conditions not detected
2
C bus format: addressing format with acknowledge bit
Slave Address Register (SAR)
SVA6
R/W
7
0
SVA5
R/W
6
0
SVA4
R/W
5
0
SVA3
R/W
4
0
Rev. 4.00 Sep 27, 2006 page 499 of 1130
SVA2
R/W
3
0
Section 16 I
SVA1
2
R/W
C bus.
2
0
2
C Bus Interface [Option]
SVA0
R/W
REJ09B0327-0400
1
0
R/W
FS
0
0
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