DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 552
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
Bit 5
MST
0
1
Bit 5
MST
0
1
Bit 4
TRS
0
1
Rev. 4.00 Sep 27, 2006 page 506 of 1130
REJ09B0327-0400
Bit 4
TRS
0
1
0
1
Description
Slave mode
[Clearing conditions]
1. When 0 is written by software
2. When bus arbitration is lost after transmission is started in I
Master mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing condition 2)
2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)
Description
Receive mode
[Clearing conditions]
1. When 0 is written by software (in cases other than setting condition 3)
2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3)
3. When bus arbitration is lost after transmission is started in I
4. When the SW bit in DDCSWR changes from 1 to 0
Transmit mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing conditions 3 and 4)
2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3
3. When a 1 is received as the R/W bit of the first frame in I
2
C Bus Interface [Option]
mode
mode
and 4)
Operating Mode
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
2
C bus format slave mode
2
2
C bus format master
C bus format master
(Initial value)
(Initial value)
(Initial value)
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