DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 631
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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18.1.3
Table 18.1 lists the input and output pins of the host interface module.
Table 18.1
Note:
Name
I/O read
I/O write
Chip select 1
Chip select 2 *
Chip select 3
Chip select 4
Command/data
Data bus
Host interrupt 1
Host interrupt 11
Host interrupt 12
Host interrupt 3
Host interrupt 4
Gate A20
HIF shutdown
* Selection of CS2 or ECS2 is by means of the CS2E bit in STCR and the FGA20E bit in
Input and Output Pins
HICR. Host interface channel 2 and the CS2 pin can be used when CS2E = 1. When
CS2E = 1, CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this
manual, both are referred to as CS2.
Host Interface Input/Output Pins
Abbreviation
IOR
IOW
CS1
CS2
ECS2
CS3
CS4
HA0
HDB7 to HDB0 P37 to
HIRQ1
HIRQ11
HIRQ12
HIRQ3
HIRQ4
GA20
HIFSD
Port
P93
P94
P95
P81
P90
PB2
PB3
P80
P30
P44
P43
P45
PB0
PB1
P81
P82
I/O
Input
Input
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Output
Output
Input
Function
Host interface read signal
Host interface write signal
Host interface chip select signal for IDR1,
ODR1, STR1
Host interface chip select signal for IDR2,
ODR2, STR2
Host interface chip select signal for IDR3,
ODR3, STR3
Host interface chip select signal for IDR4,
ODR4, STR4
Host interface address select signal.
In host read access, this signal selects the
status registers (STR1 to STR4) or data
registers (ODR1 to ODR4). In host write
access to the data registers (IDR1 to IDR3,
and IDTR4), this signal indicates whether
the host is writing a command or data.
Host interface data bus
Interrupt output 1 to host
Interrupt output 11 to host
Interrupt output 12 to host
Interrupt output 3 to host
Interrupt output 4 to host
A20 gate control signal output
Host interface shutdown control signal
Rev. 4.00 Sep 27, 2006 page 585 of 1130
Section 18 Host Interface
REJ09B0327-0400
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