MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 160

• Manufacturer Part Number: MC9S12XEP100MAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, SSI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.71
2.3.72
160
DDR0AD0
Address 0x0272
Address 0x0273
Write: Anytime.
Write: Anytime.
Field
Reset
Reset
7-0
W
W
R
R
DDR0AD07
DDR1AD07
Port AD0 data direction—
This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port AD0 Data Direction Register 0 (DDR0AD0)
Port AD0 Data Direction Register 1 (DDR1AD0)
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR0AD0 register.
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
DDR0AD06
DDR1AD06
Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0)
Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0)
0
0
6
6
Table 2-67. DDR0AD0 Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDR0AD05
DDR1AD05
0
0
5
5
DDR0AD04
DDR1AD04
NOTE
NOTE
0
0
4
4
Description
DDR0AD03
DDR1AD03
3
0
3
0
DDR0AD02
DDR1AD02
0
0
2
2
DDR0AD01
DDR1AD01
Access: User read/write
Access: User read/write
Freescale Semiconductor
0
0
1
1
DDR0AD00
DDR1AD00
0
0
0
0
(1)
(1)