MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 176

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MC9S12XEP100MAL
0
1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.98
2.3.99
176
Address 0x0375
Address 0x0376
Write: Anytime.
Write: Anytime.
WOML
PPSL
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port L pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
Port L wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or independent of the function used on the pins. If enabled the
output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of
several serial modules. These bits have no influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
WOML7
PPSL7
Port L Polarity Select Register (PPSL)
Port L Wired-Or Mode Register (WOML)
0
0
7
7
WOML6
PPSL6
0
0
6
6
Figure 2-97. Port L Wired-Or Mode Register (WOML)
Figure 2-96. Port L Polarity Select Register (PPSL)
Table 2-94. WOML Register Field Descriptions
Table 2-93. PPSL Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
WOML5
PPSL5
0
0
5
5
WOML4
PPSL4
0
0
4
4
Description
Description
WOML3
PPSL3
3
0
3
0
WOML2
PPSL2
0
0
2
2
Access: User read/write
Access: User read/write
WOML1
Freescale Semiconductor
PPSL1
0
0
1
1
WOML0
PPSL0
0
0
0
0
(1)
(1)

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