MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 331

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte
by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access
size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match.
Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs
to comparator register contents or when the data bus is equivalent to the comparator register contents.
8.4.2.2
Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match
qualification functions the same as for comparators A and C.
If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the
specified type of access causes a match. Thus if configured for a byte access of a particular address, a word
access covering the same address does not lead to match.
8.4.2.3
Comparators A and C each feature an NDB control bit, which allows data bus comparators to be configured
to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the
contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGxDHM/DBGxDLM), so that it is ignored in the comparison. A
match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register
bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any
data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored
and prevents a match because no difference can be detected. In this case address bus equivalence does not
cause a match.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address used in the code.
Comparators
Comparators
Comparators
Comparators
Comparator
A and C
B and D
B and D
B and D
Exact Address Comparator Match (Comparators B and D)
Data Bus Comparison NDB Dependency
Table 8-40. Comparator Access Size Considerations
Address
ADDR[n]
ADDR[n]
ADDR[n]
ADDR[n]
MC9S12XE-Family Reference Manual Rev. 1.23
SZE
0
1
1
SZ8
NOTE
X
0
1
Word and byte accesses of ADDR[n]
Word and byte accesses of ADDR[n]
Word accesses of ADDR[n]
Condition For Valid Match
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
Byte accesses of ADDR[n]
MOVB #$BYTE ADDR[n]
MOVB #$BYTE ADDR[n]
MOVB #$BYTE ADDR[n]
Chapter 8 S12X Debug (S12XDBGV3) Module
1
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