MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 766

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Chapter 21 Serial Peripheral Interface (S12SPIV5)
21.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
21.2.4
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
21.3
This section provides a detailed description of address space and registers used by the SPI.
21.3.1
The memory map for the SPI is given in
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
766
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reserved
Reserved
Register
SPIDRH
SPICR1
SPICR2
SPIDRL
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
SPIBR
SPISR
Name
Memory Map and Register Definition
SS — Slave Select Pin
SCK — Serial Clock Pin
Module Memory Map
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
Bit 7
SPIE
SPIF
R15
T15
R7
T7
0
0
= Unimplemented or Reserved
SPPR2
XFRW
SPE
MC9S12XE-Family Reference Manual , Rev. 1.23
R14
T14
R6
T6
6
0
Figure 21-2. SPI Register Summary
Figure
SPPR1
SPTEF
SPTIE
R13
T13
R5
T5
5
0
21-2. The address listed for each register is the sum of a
MODFEN
SPPR0
MSTR
MODF
R12
T12
R4
T4
4
BIDIROE
CPOL
R11
T11
R3
T3
3
0
0
CPHA
SPR2
R10
T10
R2
T2
2
0
0
Freescale Semiconductor
SPISWAI
SSOE
SPR1
R9
R1
T9
T1
1
0
LSBFE
SPC0
SPR0
Bit 0
R8
T8
R0
T0
0

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