DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 1023
DF2378RVFQ34WV
Manufacturer Part Number
DF2378RVFQ34WV
Description
MCU 3V 512K I-TEMP PB-FREE 144-L
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378RVFQ34WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 1023 of 1208
- Download datasheet (8Mb)
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (
internal clocks.
The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider.
Figure 23.1 shows a block diagram of the clock pulse generator.
The frequency can be changed by means of the PLL circuit. Frequency changes are made by
software by means of settings in the PLL control register (PLLCR) and the system clock control
register (SCKCR).
23.1
The clock pulse generator has the following registers.
• System clock control register (SCKCR)
• PLL control register (PLLCR)
23.1.1
SCKCR controls
used by the PLL circuit is changed, and the division ratio used by the divider.
CPG0400A_010020020400
Legend:
PLLCR: PLL system control register
SCKCR: System clock control register
EXTAL
XTAL
Register Descriptions
System Clock Control Register (SCKCR)
Oscillator
φ
clock output and selects operation when the frequency multiplication factor
Figure 23.1 Block Diagram of Clock Pulse Generator
Section 23 Clock Pulse Generator
PLL circuit
(×1, 2, 4)
PLLCR
STC0, STC1
Rev.7.00 Mar. 18, 2009 page 955 of 1136
Divider
SCKCR
SCK2 to SCK0
Section 23 Clock Pulse Generator
System clock
to φ pin
REJ09B0109-0700
Internal clock
to peripheral
modules
φ
) and
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