DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 205
DF2378RVFQ34WV
Manufacturer Part Number
DF2378RVFQ34WV
Description
MCU 3V 512K I-TEMP PB-FREE 144-L
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378RVFQ34WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 205 of 1208
- Download datasheet (8Mb)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC) * , and data
transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
Note: * The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
6.1
• Manages external address space in area units
• Basic bus interface
• Burst ROM interface
• DRAM interface
• Synchronous DRAM interface *
• Bus arbitration function
Note: * The Synchronous DRAM interface is not supported by the H8S/2378 Group.
BSCS201A_010020020400
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, DRAM, or synchronous DRAM interface * can be set
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
Burst ROM interface can be set independently for areas 0 and 1
DRAM interface can be set for areas 2 to 5
Continuous synchronous DRAM space can be set for areas 2 to 5
Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and
EXDMAC
Features
H8S/2373R.
Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 137 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700
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