DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 373
DF2377RVFQ33
Manufacturer Part Number
DF2377RVFQ33
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)
DTC
Second transfer area
using chain transfer
First transfer area
Rev.7.00 Mar. 18, 2009 page 305 of 1136
DMACR_0A
DMACR_1A
DMAWER
Section 7 DMA Controller (DMAC)
ETCR_0A
ETCR_0B
ETCR_1A
ETCR_1B
IOAR_0A
IOAR_0B
IOAR_1A
IOAR_1B
MAR_0A
MAR_0B
MAR_1A
MAR_1B
DMABCR
DMACR_0B
DMACR_1B
DMATCR
REJ09B0109-0700
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