DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 1036
![IC H8S MCU FLASH 3V 384K 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
DF2377RVFQ33W
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Section 24 Power-Down Modes
24.1
The registers relating to the power-down mode are shown below. For details on the system clock
control register (SCKCR), refer to section 23.1.1, System Clock Control Register (SCKCR).
• System clock control register (SCKCR)
• Standby control register (SBYCR)
• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)
• Extension module stop control register H (EXMSTPCRH)
• Extension module stop control register L (EXMSTPCRL)
24.1.1
SBYCR performs software standby mode control.
Bit
7
6
Rev.7.00 Mar. 18, 2009 page 968 of 1136
REJ09B0109-0700
Bit Name
SSBY
OPE
Register Descriptions
Standby Control Register (SBYCR)
Initial Value
0
1
R/W
R/W
R/W
Description
Software Standby
This bit specifies the transition mode after
executing the SLEEP instruction
0: Shifts to sleep mode after the SLEEP instruction
1: Shifts to software standby mode after the SLEEP
This bit does not change when clearing the
software standby mode by using external interrupts
and shifting to normal operation. This bit should be
written 0 when clearing.
Output Port Enable
Specifies whether the output of the address bus
and bus control signals (CS0 to CS7, AS, RD,
HWR, LWR, UCAS, LCAS) is retained or set to the
high-impedance state in software standby mode.
0: In software standby mode, address bus and bus
1: In software standby mode, address bus and bus
is executed
instruction is executed
control signals are high-impedance
control signals retain output state
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