DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 114
![IC H8S MCU FLASH 3V 384K 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
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Quantity
Price
Company:
Part Number:
DF2377RVFQ33W
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Section 2 CPU
2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
7
6
5
4
3
2
Rev.7.00 Mar. 18, 2009 page 46 of 1136
REJ09B0109-0700
Bit Name
I
UI
H
U
N
Z
Condition-Code Register (CCR)
Initial Value
1
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
For details, refer to section 5, Interrupt Controller.
User Bit or Interrupt Mask Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
For this LSI, Interrupt Mask Bit is not available.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is
a carry or borrow at bit 27, and cleared to 0 otherwise.
User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
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