DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 227
![IC H8S MCU FLASH 3V 384K 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2377RVFQ33W
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Bit
6
5
Bit Name
RCDM
DDS
Initial Value
0
0
R/W
R/W
R/W
Description
RAS Down Mode
When access to DRAM space is interrupted by an
access to normal space, an access to an internal
I/O register, etc., this bit selects whether the RAS
signal is held low while waiting for the next DRAM
access (RAS down mode), or is driven high again
(RAS up mode). The setting of this bit is valid only
when the BE bit is set to 1.
If this bit is cleared to 0 when set to 1 in the RAS
down state, the RAS down state is cleared at that
point, and RAS goes high.
When continuous synchronous DRAM space is set,
reading from and writing to this bit is enabled.
However, the setting does not affect the operation.
0: RAS up mode selected for DRAM space access
1: RAS down mode selected for DRAM space
DMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when DMAC single
address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst access,
DMAC single address transfer is performed in full
access mode regardless of the setting of this bit.
This bit has no effect on other bus master external
accesses or DMAC dual address transfers.
0: Full access is always executed
1: Burst access is enabled
access
Rev.7.00 Mar. 18, 2009 page 159 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700
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