DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 336
![IC H8S MCU FLASH 3V 384K 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Company:
Part Number:
DF2377RVFQ33W
Manufacturer:
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Quantity:
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Section 6 Bus Controller (BSC)
6.9.2
Table 6.12 shows the pin states in an idle cycle.
Table 6.12 Pin States in Idle Cycle
Pins
A23 to A0
D15 to D0
CSn (n = 7 to 0)
UCAS, LCAS
AS
RD
(OE)
HWR, LWR
DACKn (n = 1, 0)
EDACKn (n = 3, 2)
Notes: 1. Remains low in DRAM space RAS down mode.
6.10
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.
Figure 6.83 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or DMA single address mode transfer continues
for two states or longer, and there is an internal access next, an external write only is executed in
the first state, but from the next state onward an internal access (on-chip memory or internal I/O
register read/write) is executed in parallel with the external address space write rather than waiting
until it ends.
Rev.7.00 Mar. 18, 2009 page 268 of 1136
REJ09B0109-0700
2. Remains low in a DRAM space refresh cycle.
Pin States in Idle Cycle
Write Data Buffer Function
Pin State
Contents of following bus cycle
High impedance
High *
High *
High
High
High
High
High
High
1
2
*
2
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