DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 597
![IC H8S MCU FLASH 3V 384K 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
DF2377RVFQ33W
Manufacturer:
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Quantity:
10 000
Company:
Part Number:
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Manufacturer:
Renesas Electronics America
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10.14.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F.
PFDDR cannot be read; if it is, an undefined value will be read.
Bit
7
6
5
4
3
2
1
0
Note:
Bit Name
PF7DDR
PF6DDR
PF5DDR
PF4DDR
PF3DDR
PF2DDR
PF1DDR
PF0DDR
* PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in mode 7.
Initial Value
1/0 *
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Description
•
•
Modes 7 (when EXPE = 1), 1, 2, and 4
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when
ASOE is set to 1. When ASOE is cleared to 0, pin
PF6 is an I/O port and its function can be
switched with PF6DDR.
Pins PF5 and PF4 are automatically designated
as bus control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when
LWROE is set to 1. When LWROE is cleared to
0, pin PF3 is an I/O port and its function can be
switched with PF3DDR.
Pins PF2 to PF0 function as bus control
input/output pins (LCAS, UCAS, and WAIT) when
the appropriate bus controller settings are made.
Otherwise, these pins are output ports when
PFDDR is set to 1 and are input ports when
PFDDR is cleared to 0.
Mode 7 (when EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions
can be switched with PFDDR.
Rev.7.00 Mar. 18, 2009 page 529 of 1136
Section 10 I/O Ports
REJ09B0109-0700
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