DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 450
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 Programmable Timing Pattern Controller
11.4
11.4.1
TP
DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The
data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
11.4.2
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
Figure 11.9 illustrates the non-overlapping TPC output operation.
Rev. 3.00 Mar 21, 2006 page 420 of 814
REJ09B0302-0300
TPC output pin
0
if their value is 1.
to TP
15
Usage Notes
Operation of TPC Output Pins
Note on Non-Overlapping Output
are multiplexed with ITU, DMAC, address bus, and other pin functions. When ITU,
DDR
Q
Figure 11.9 Non-Overlapping TPC Output
Q
NDER
Q
DR
C
D
Compare match A
Compare match B
Q
NDR
D
Internal
data bus
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