HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1010

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
Bit 4—Prescaler Select (PSS): This bit selects the clock source input to WDT1 TCNT.
It also controls operation when shifting low power dissipation modes. The operating mode
selected after the SLEEP instruction is executed is determined in combination with other control
bits.
For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register
(TCSR), and this section.
Bit 4
PSS
0
1
Notes: 1. Always set high-speed mode when shifting to watch mode or subactive mode.
Page 960 of 1458
2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and
Description
•
•
•
•
•
H8S/2635 Group. In versions other than the U-mask and W-mask versions, and
H8S/2635 Group, however, the PSS bit must always be written with 0 since no subclock
functions are available.
TCNT counts the divided clock from the φ -based prescaler (PSM).
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode or software standby mode.
TCNT counts the divided clock from the φsubclock-based prescaler (PSS).
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, watch mode *
When the SLEEP instruction is executed in subactive mode *
subsleep mode *
2
, watch mode *
2
, or high-speed mode.
1
*
2
, or subactive mode *
H8S/2639, H8S/2638, H8S/2636,
2
, operation shifts to
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
(Initial value)
May 28, 2010
1
*
2
.