HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1219

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
IRR0—Interrupt Register
IRR1—Interrupt Register
Note: * This register is not available in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Overload Frame Interrupt Flag
Bit
Initial value
Read/Write
0
1
[Clearing condition]
• Writing 1
Overload frame transmission
[Setting condition]
• Overload frame is transmitted
Bus Off Interrupt Flag
0
1
[Clearing condition]
• Writing 1
Bus off state caused by transmit error
[Setting condition]
• When TEC ≥ 256
IRR7
R/W
15
0
Error Passive Interrupt Flag
0
1
[Clearing condition]
• Writing 1
Error passive state caused by transmit/receive error
[Setting condition]
• When TEC ≥ 128 or REC ≥ 128
IRR6
R/W
14
Receive Overload Warning Interrupt Flag
0
0
1
[Clearing condition]
• Writing 1
Error warning state caused by receive error
[Setting condition]
• When REC ≥ 96
Transmit Overload Warning Interrupt Flag
0
1
IRR5
R/W
13
0
[Clearing condition]
• Writing 1
Error warning state caused by transmit error
[Setting condition]
• When TEC ≥ 96
Remote Frame Request Interrupt Flag
0
1
[Clearing condition]
• Clearing of all bits in RFPR (remote request register) of mailbox for which
Remote frame received and stored in mailbox
[Setting condition]
• When remote frame reception is completed, when corresponding MBIMR = 0
Receive Message Interrupt Flag
IRR4
receive interrupt requests are enabled by MBIMR
0
1
R/W
12
0
[Clearing condition]
• Clearing of all bits in RXPR (receive complete register) of mailbox
Data frame or remote frame received and stored in mailbox
[Setting condition]
• When data frame or remote frame reception is completed, when
for which receive interrupt requests are enabled by MBIMR
corresponding MBIMR = 0
Note: * After reset or hardware standby release, the module stop bit is
Reset Interrupt Flag
0
1
[Clearing condition]
• Writing 1
Hardware reset (HCAN module stop*, software standby)
[Setting condition]
• When reset processing is completed after a hardware reset
(HCAN module stop*, software standby)
H'F812
H'FA12
initialized to 1, and so the HCAN enters the module stop state.
IRR3
R/W
11
0
IRR2
10
R
0
Appendix B Internal I/O Register
IRR1
R
9
0
Page 1169 of 1458
IRR0
R/W
8
1
HCAN1 *
HCAN0