HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1415

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TCR0—Timer Control Register 0
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value
Read/Write
Counter Clear
Notes: 1.
0
1
CCLR2
0
1
0
1
R/W
7
0
2.
0
1
0
1
0
1
0
1
Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture *
TCNT cleared by TGRD compare match/input capture *
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
CCLR1
R/W
6
0
Note: Internal clock edge selection is valid when the input clock
Clock Edge
0
1
⎯
0
1
CCLR0
is φ/4 or slower. This setting is ignored if the input clock is φ/1,
or when overflow/underflow of another channel is selected.
R/W
Count at rising edge
Count at falling edge
Count at both edges
5
0
Time Prescaler
0
1
CKEG1
0
1
0
1
R/W
4
0
0
1
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
CKEG0
R/W
H'FF10
3
0
TPSC2
R/W
2
0
Appendix B Internal I/O Register
TPSC1
R/W
1
0
2
2
1
1
TPSC0
Page 1365 of 1458
R/W
0
0
TPU0