HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1442

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Register
ICSR0—I
ICSR1—I
Page 1392 of 1458
2
2
C Bus Status Register
C Bus Status Register
Bit
Initial value
R/W
Notes: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I
Error stop condition detection flag
:
:
:
0 No error stop condition
1 • Error stop condition detected in slave mode in I
[Clearings]
(1) When 0 written after reading ESTP=1;
(2) When IRIC flag is cleared to 0.
[Setting]
On detection of stop condition while sending frame.
• No meaning when in other than slave mode in I
R/(W)*
* Only 0 can be written to these bits (to clear these flags).
ESTP
7
0
Normal end condition detection flag
0 No normal end condition
1 Normal end condition detected in slave mode in I
[Clearings]
(1) When 0 is written after reading STOP=1;
(2) When IRIC flag is cleared to 0.
[Setting]
On detection of stop condition on completion of sending frame.
• No meaning when in other than slave mode in I
R/(W)*
STOP
6
0
I
2
C bus interface continuous transmit and receive interrupt request flag
0 Transmit wait state, or transmitting
1 Continuous transmit state
[Clearings]
(1) When 0 written after reading IRTR=1;
(2) When IRIC flag is cleared to 0.
[Settings]
• In I
• In other than I
R/(W)*
When 1 is set in TDRE or RDRF flag when AASX=1.
When TDRE or RDRF flag is set to 1.
IRTR
5
0
2
C bus interface slave mode
2nd slave address confirmation flag
0 2nd slave address not confirmed
1 2nd slave address confirmed
[Clearings]
(1) When 0 is written after reading AASX=1;
(2) When start conditions are detected;
(3) In master mode.
[Setting]
• When 2nd slave address is detected in slave receive mode and FSX = 0.
R/(W)*
AASX
2
C bus interface slave mode
4
0
Arbitration lost flag
0 Secure bus.
1 Bus arbitration lost
2
2
C bus format
C bus format
[Clearings]
(1) When data is written to ICDR (when sending), or when data is read (when
(2) When 0 is written after reading AL=1.
[Settings]
(1) When there is a mismatch between internal SDA and SDA pin at rise in SCL
(2) When the internal SCL level is HIGH at the fall in SCL in master transmit mode.
R/(W)*
AL
receiving);
in master transmit mode;
3
0
Slave address confirmation flag
0 Slave address or general call address not confirmed
1 Slave address or general call address confirmed
2
2
C bus format
C bus format
[Clearings]
(1) When data is written to ICDR (when sending), or when data is
(2) When 0 is written after reading AAS=1;
(3) In master mode.
[Setting]
• When slave address or general call address is detected in slave
R/(W)*
AAS
receive mode and FS = 0.
read from ICDR (when receiving);
2
0
General call address confirmation flag
0 General call address not confirmed
1 General call address confirmation
[Clearings]
(1) When data is written to ICDR (when sending), or when data is
(2) When 0 is written after reading ADZ=1;
(3) In master mode.
[Setting]
• When general call address is detected is in slave receive mode and
R/(W)*
ADZ
FSX = 0 or FS = 0).
read from ICDR (when receiving);
1
0
Acknowledge bit
H'FF79
H'FF81
0 When receiving, 0 is output at acknowledge output timing.
1 When receiving, 1 is output at acknowledge output timing.
When transmitting, this bit shows that an acknowledge (0)
has not been sent from the receiving device.
When transmitting, this bit shows that an acknowledge (1)
has been sent from the receiving device.
ACKB
R/W
0
0
2
C bus interface option added.
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010
IIC0
IIC1