HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1447

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
SSR0—Serial Status Register 0
SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value
Read/Write
Transmit Data Register Empty
0 [Clearing conditions]
1 [Setting conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
R/(W)*
TDRE
7
1
R/(W)*
RDRF
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
Receive Data Register Full
6
0
0 [Clearing conditions]
1 [Setting condition]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
• When serial reception ends normally and receive data is transferred from RSR to RDR
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
R/(W)*
ORER
Overrun Error
0 [Clearing condition]
1 [Setting condition]
5
0
• When 0 is written in ORER after reading ORER = 1 *
• When the next serial reception is completed while RDRF = 1 *
Framing Error
0 [Clearing condition]
1 [Setting condition]
• When 0 is written in FER after reading FER = 1 *
• When the SCI checks the stop bit at the end of the receive data
R/(W)*
when reception ends, and the stop bit is 0 *
FER
4
0
Parity Error
0 [Clearing condition]
1 [Setting condition]
• When 0 is written in PER after reading PER = 1 *
• When, in reception, the number of 1 bits in the receive
R/(W)*
Transmit End
PER
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR*
0 [Clearing conditions]
1 [Setting conditions]
H'FF7C
H'FF84
H'FF8C
3
0
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
writes data to TDR
a 1-byte serial transmit character
TEND
Multiprocessor Bit
R
2
1
0 [Clearing condition]
1 [Setting condition]
• When data with a 0 multiprocessor
• When data with a 1 multiprocessor
Multiprocessor Bit Transfer
bit is received *
bit is received
0 Data with a 0 multi-processor
1 Data with a 1 multi-processor
4
bit is transmitted
bit is transmitted
Appendix B Internal I/O Register
MPB
1
3
R
1
0
7
2
MPBT
R/W
6
0
0
5
Page 1397 of 1458
SCI0
SCI1
SCI2