HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 182
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Quantity
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Section 5 Interrupt Controller
5.5.4
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
5.5.5
When operating by clock input, acceptance of input to an IRQ pin is synchronized with the clock.
In software standby mode, the input is accepted asynchronously. For details on the input
conditions, see section 24.5.2, Control Signal Timing.
5.5.6
When the system is operating normally under conditions conforming to the specified electrical
properties, exception processing by the on-chip interrupt controller linked to the CPU is used to
execute the NMI interrupt. When operation is not normal (runaway status) due to a software
problem or abnormal input to one of the LSI’s pins, no operations can be guaranteed, including the
NMI interrupt. In such cases it is possible to cause the LSI to return to normal program execution
by applying an external reset.
Page 132 of 1458
L1:
Interrupts during Execution of EEPMOV Instruction
IRQ Interrupts
Notes on Use of NMI Interrupt
EEPMOV.W
MOV.W
BNE
R4,R4
L1
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010
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