HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 187

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Note: The H8S/2635 Group is not equipped with a PBC.
6.1
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:
instruction fetch, data read, data write, and data read/write.
6.1.1
The PC break controller has the following features:
• Two break channels (A and B)
• The following can be set as break compare conditions:
• The timing of PC break exception handling after the occurrence of a break condition is as
• Module stop mode can be set
REJ09B0103-0800 Rev. 8.00
May 28, 2010
⎯ 24 address bits
⎯ Bus cycle
⎯ Bus master
follows:
⎯ Immediately before execution of the instruction fetched at the set address (instruction
⎯ Immediately after execution of the instruction that accesses data at the set address (data
⎯ The initial setting is for PBC operation to be halted. Register access is enabled by clearing
Bit masking possible
Instruction fetch
Data access: data read, data write, data read/write
Either CPU or CPU/DTC can be selected
fetch)
access)
module stop mode.
Overview
Features
Section 6 PC Break Controller (PBC)
Section 6 PC Break Controller (PBC)
Page 137 of 1458

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