HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 196

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
6.3.5
If a PC break interrupt is generated when the following operations are being performed, exception
handling is executed on completion of the specified transfer.
(1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction:
(2) When a PC break interrupt is generated at a DTC transfer address:31
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Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available
Execution of instruction
after sleep instruction
PC break exception
SLEEP instruction
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
execution
handling
in the U-mask and W-mask versions only.
(A)
PC Break Operation in Continuous Data Transfer
Figure 6-2 Operation in Power-Down Mode Transitions
Execution of instruction
after sleep instruction
PC break exception
exception handling
SLEEP instruction
Direct transition*
System clock
→ subclock*
execution
handling
(B)
Subactive*
mode
Execution of instruction
oscillation settling time
after sleep instruction
PC break exception
exception handling
SLEEP instruction
Direct transition*
Subclock* →
system clock,
execution
handling
(C)
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
High-speed
(medium-speed)
mode
SLEEP instruction
respective mode
Transition to
execution
(D)
May 28, 2010