HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 232

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Bus Controller
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7-15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Page 182 of 1458
CS* (area B)
CS* (area A)
Note: * The CS signal is generated externally rather than inside the LSI device.
Address bus
Data bus
RD
φ
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
Figure 7-15 Example of Idle Cycle Operation (1)
T
2
T
Long output
floating time
3
Bus cycle B
T
1
T
2
Data
collision
CS* (area A)
CS* (area B)
Address bus
Data bus
RD
φ
T
1
(b) Idle cycle inserted
Bus cycle A
(Initial value ICIS1 = 1)
T
2
H8S/2639, H8S/2638, H8S/2636,
T
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
3
T
Bus cycle B
I
T
1
May 28, 2010
T
2