HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 234

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Bus Controller
(3) Relationship between Chip Select (CS * ) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal * . An
example is shown in figure 7-17.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Note: * The CS signal is generated externally rather than inside the LSI device.
Page 184 of 1458
CS* (area A)
CS* (area B)
Note: * The CS signal is generated externally rather than inside the LSI device.
Address bus
Data bus
HWR
RD
φ
Figure 7-17 Relationship between Chip Select (CS) * and Read (RD)
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS0 = 0)
T
2
T
floating time
3
Long output
Bus cycle B
T
1
T
2
Data
collision
CS* (area A)
CS* (area B)
Address bus
Data bus
HWR
RD
φ
T
(b) Idle cycle inserted
1
Bus cycle A
(Initial value ICIS0 = 1)
T
2
H8S/2639, H8S/2638, H8S/2636,
T
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
3
T
I
Bus cycle B
T
1
May 28, 2010
T
2