HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 32

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
6.1
6.2
6.3
Section 7 Bus Controller
7.1
7.2
7.3
Page xxxii of l
5.6.3
Overview........................................................................................................................... 137
6.1.1
6.1.2
6.1.3
Register Descriptions ........................................................................................................ 139
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Operation .......................................................................................................................... 143
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Overview........................................................................................................................... 149
7.1.1
7.1.2
7.1.3
7.1.4
Register Descriptions ........................................................................................................ 152
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
Overview of Bus Control .................................................................................................. 163
7.3.1
7.3.2
7.3.3
7.3.4
Operation ............................................................................................................. 134
Features................................................................................................................ 137
Block Diagram..................................................................................................... 138
Register Configuration......................................................................................... 139
Break Address Register A (BARA) ..................................................................... 139
Break Address Register B (BARB) ..................................................................... 140
Break Control Register A (BCRA) ...................................................................... 140
Break Control Register B (BCRB) ...................................................................... 142
Module Stop Control Register C (MSTPCRC).................................................... 142
PC Break Interrupt Due to Instruction Fetch ....................................................... 143
PC Break Interrupt Due to Data Access............................................................... 144
Notes on PC Break Interrupt Handling ................................................................ 144
Operation in Transitions to Power-Down Modes ................................................ 145
PC Break Operation in Continuous Data Transfer............................................... 146
When Instruction Execution Is Delayed by One State......................................... 147
Additional Notes .................................................................................................. 148
Features................................................................................................................ 149
Block Diagram..................................................................................................... 150
Pin Configuration................................................................................................. 151
Register Configuration......................................................................................... 151
Bus Width Control Register (ABWCR)............................................................... 152
Access State Control Register (ASTCR) ............................................................. 153
Wait Control Registers H and L (WCRH, WCRL).............................................. 154
Bus Control Register H (BCRH) ......................................................................... 158
Bus Control Register L (BCRL) .......................................................................... 160
Pin Function Control Register (PFCR) ................................................................ 161
Area Partitioning.................................................................................................. 163
Bus Specifications ............................................................................................... 164
Memory Interfaces............................................................................................... 165
Interface Specifications for Each Area ................................................................ 166
................................................................................................... 149
........................................................................... 137
REJ09B0103-0800 Rev. 8.00
May 28, 2010