HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 355

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Note: The H8S/2635 Group is not equipped with a DTC or a PPG.
10.1
The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.
10.1.1
• Maximum 16-pulse input/output
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
REJ09B0103-0800 Rev. 8.00
May 28, 2010
⎯ A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
⎯ TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
⎯ Waveform output at compare match: Selection of 0, 1, or toggle output
⎯ Input capture function: Selection of rising edge, falling edge, or both edge detection
⎯ Counter clear operation: Counter clearing possible by compare match or input capture
⎯ Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
⎯ Simultaneous clearing by compare match and input capture possible
⎯ Register simultaneous input/output possible by counter synchronous operation
⎯ PWM mode: Any PWM output duty can be set
⎯ Maximum of 15-phase PWM output possible by combination with synchronous operation
⎯ Input capture register double-buffering possible
⎯ Automatic rewriting of output compare register possible
⎯ Two-phase encoder pulse up/down-count possible
⎯ Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel
⎯ Fast access is possible via a 16-bit bus interface
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
4) overflow/underflow
Overview
Features
Section 10 16-Bit Timer Pulse Unit (TPU)
Section 10 16-Bit Timer Pulse Unit (TPU)
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