HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 37

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.3 Operation .......................................................................................................................... 413
11.4 Usage Notes ...................................................................................................................... 422
Section 12 Watchdog Timer
12.1 Overview........................................................................................................................... 425
12.2 Register Descriptions ........................................................................................................ 429
12.3 Operation .......................................................................................................................... 439
12.4 Interrupts ........................................................................................................................... 443
12.5 Usage Notes ...................................................................................................................... 443
Section 13 Serial Communication Interface (SCI)
13.1 Overview........................................................................................................................... 445
REJ09B0103-0800 Rev. 8.00
May 28, 2010
11.2.8 Module Stop Control Register A (MSTPCRA) ................................................... 412
11.3.1 Overview.............................................................................................................. 413
11.3.2 Output Timing...................................................................................................... 414
11.3.3 Normal Pulse Output............................................................................................ 415
11.3.4 Non-Overlapping Pulse Output............................................................................ 417
11.3.5 Inverted Pulse Output .......................................................................................... 420
11.3.6 Pulse Output Triggered by Input Capture ............................................................ 421
12.1.1 Features................................................................................................................ 425
12.1.2 Block Diagram..................................................................................................... 426
12.1.3 Pin Configuration................................................................................................. 428
12.1.4 Register Configuration......................................................................................... 428
12.2.1 Timer Counter (TCNT)........................................................................................ 429
12.2.2 Timer Control/Status Register (TCSR)................................................................ 430
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 436
12.2.4 Notes on Register Access..................................................................................... 437
12.3.1 Watchdog Timer Operation ................................................................................. 439
12.3.2 Interval Timer Operation ..................................................................................... 441
12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 441
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 442
12.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 443
12.5.2 Changing Value of PSS* and CKS2 to CKS0 ..................................................... 444
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 444
12.5.4 Internal Reset in Watchdog Timer Mode............................................................. 444
12.5.5 OVF Flag Clearing in Interval Timer Mode ........................................................ 444
13.1.1 Features................................................................................................................ 445
13.1.2 Block Diagram..................................................................................................... 447
13.1.3 Pin Configuration................................................................................................. 448
13.1.4 Register Configuration......................................................................................... 449
............................................................................................. 425
.................................................... 445
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