HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 494

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 12 Watchdog Timer
12.5.2
If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could
occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)
before changing the value of bits PSS * and CKS2 to CKS0.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
12.5.3
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
12.5.4
The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, but TCNT and TSCR of the WDT are reset.
12.5.5
If conflict occurs between OVF flag clearing and OVF flag reading in interval timer mode, the
flag may not be cleared by writing 0 to OVF even though the OVF = 1 state has been read. When
interval timer interrupts are disabled and the OVF flag is polled, for instance, and there is a
possibility of conflict between OVF flag setting and reading, the OVF = 1 state should be read at
least twice before writing 0 to OVF in order to clear the flag.
Page 444 of 1458
U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions.
Changing Value of PSS* and CKS2 to CKS0
Switching between Watchdog Timer Mode and Interval Timer Mode
Internal Reset in Watchdog Timer Mode
OVF Flag Clearing in Interval Timer Mode
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010

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