HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 505

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 13.2.8, Bit Rate Register (BRR).
Bit 1
CKS1
0
1
13.2.6
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset and in standby mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE
0
1
Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value
R/W
clearing it to 0, or clearing the TIE bit to 0.
Serial Control Register (SCR)
Bit 0
CKS0
0
1
0
1
Description
Transmit data empty interrupt (TXI) requests disabled*
Transmit data empty interrupt (TXI) requests enabled
:
:
:
R/W
TIE
7
0
Description
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
Section 13 Serial Communication Interface (SCI)
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(Initial value)
(Initial value)
Page 455 of 1458
CKE0
R/W
0
0