HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 511

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER
0
1
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 3
PER
0
1
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
cleared to 0.
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
cleared to 0.
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In clocked synchronous mode, serial transmission cannot be continued, either.
Description
[Clearing condition]
•
[Setting condition]
•
Description
[Clearing condition]
•
[Setting condition]
•
When 0 is written to FER after reading FER = 1
When the SCI checks whether the stop bit at the end of the receive data when
reception ends, and the stop bit is 0 *
When 0 is written to PER after reading PER = 1
When, in reception, the number of 1 bits in the receive data plus the parity bit does
not match the parity setting (even or odd) specified by the O/E bit in SMR *
2
Section 13 Serial Communication Interface (SCI)
(Initial value) *
(Initial value) *
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